One type of prior non-volatile semiconductor memory is the flash electrically erasable programmable read-only memory ("flash memory"). The flash memory can be programmed by a user, and once programmed, the flash memory retains its data until erased. After erasure, the flash memory may be programmed with new code or data.
Flash memories differ from conventional electrically erasable programmable read only memory ("EEPROMs") with respect to erasure. Conventional EEPROMs typically use a select transistor for individual byte erase control. Flash memories, on the other hand, typically achieve much higher density with single transistor cells. During one prior art flash memory erase method, a high voltage is supplied to the sources of every memory cell in a memory array simultaneously. This results in a full array erasure.
For one prior flash EEPROM, a logical "one" means that few if any electrons are stored on a floating gate associated with a bit cell. A logical "zero" means that many electrons are stored on the floating gate associated with the bit cell. Erasure of that prior flash memory causes a logical one to be stored in each bit cell. Every cell of that flash memory can only be written from a logical zero to a logical one by erasure of the entire array. Bit cells of the prior flash memory can, however, be individually overwritten from a logical one to a logical zero, given that this entails simply adding electrons to a floating gate that contains the intrinsic number of electrons associated with the erased state.
One prior flash EEPROM is the 28F256 complementary metal oxide semiconductor ("CMOS") flash memory sold by Intel Corporation of Santa Clara, Calif., which is a 256 kilobit flash EEPROM. The 28F256 flash memory includes a command register to manage electrical erasure and reprogramming. Commands are written to the command register from a controlling microprocessor using standard microprocessor write timings. The command register contents serve as input to an internal state machine that controls erase and programming circuitry.
The controlling microprocessor controls the erasure and programming of the flash memory. A prior Quick-Erase.TM. algorithm of Intel Corporation can be used by the microprocessor to erase the flash memory. The prior Quick-Erase.TM. algorithm requires that all bits first be programmed to their charged state, that is, each bit of data must be equal to 0. Erasure then proceeds by pulling the sources of the flash transistors in the array up to a high voltage level for a period of 10 msec, while keeping the transistor gates at zero volts. After each erase operation, byte verification is performed. Proper device operation requires that the erasure procedure be strictly followed.
The prior Quick-Pulse Programming.TM. algorithm of Intel Corporation can be used to then program the flash memory. The Quick-Pulse Programming.TM. algorithm requires that a programming pulse of a specific duration and voltage level be applied to the program power supply Vpp and the device power supply Vcc. For example, for certain prior Intel flash memories a programming pulse of 10 .mu.sec has been suggested while Vpp is held at 12.75. After the programming pulse is applied, the user must verify whether the memory cell addressed is properly programmed. If not properly programmed, a programming pulse may be reapplied a number of times before a programming error is recognized. Proper and reliable operation of the flash memory mandates that the programming procedure be strictly followed.
One disadvantage of this prior method of controlling erasure and programming using a microprocessor is that it ties up the microprocessor, thus requiring a relatively high level of microprocessor overhead. This, in turn, decreases system throughput.
Another disadvantage of the prior way of controlling erasure and programming of the flash memory using a microprocessor is the relatively high complexity of typical erasure/programming software. This complex software requires a relatively high level of user sophistication. Moreover, this complex software increases the likelihood of a customer error, such as over-erasure of the flash memory.
Another prior flash memory is the 28F001 CMOS flash memory sold by Intel Corporation of Santa Clara, Calif. The 28F001 is a 1 megabit flash memory, which incorporates a prior write state machine. The prior write state machine automatically programs and erases the array upon receipt of a two stage command from the command port. The prior write state machine thus simplifies erasure and programming for flash memory users. The prior write state machine increases system throughput by freeing the controlling microprocessor for other tasks.
The prior write state machine executes both erase and program commands using a single algorithm. The algorithm manages several prior peripheral circuits to execute program and erase commands.
A disadvantage of the algorithm of the prior write state machine is its complexity and lack of flexibility. The erase portion of the algorithm cannot be modified without effecting the program portion, and vice versa. Further, modifications to the algorithm cannot be made without also modifying the prior peripheral circuits. Also, handling both erasure and programming via a single algorithm makes it difficult to optimize both erasure and programming.
Another disadvantage of the prior write state machine is that it does not permit the repair or replacement of shorted rows within the memory array. Prior flash memories including shorted rows must be discarded.